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INTEGRATED CIRCUITS
PCA8550 4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
Product specification 1998 Sep 29
Philips Semiconductors
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
FEATURES
*4-bit 2-to-1 multiplexer, 1-bit latch *5-bit internal non-volatile register *Override input forces all outputs to logic 0 *Internal non-volatile register write/readable via I2C bus *Write-protect pin enables/disables I2C writes to register *2.5V multiplexed outputs *3.3V non-multiplexed output (latched) *5V tolerant inputs *Useful for 'jumperless' configuration of PC motherboards *Designed for use in Pentium Pro/Pentium IITM systems
Pentium II is a registered trademark of Intel Corporation
PIN CONFIGURATION
2 IC
SCL 1
16 VCC 15 WP 14 NON_MUXED_OUT 13 MUX_SELECT 12 MUX_OUT A 11 MUX_OUT B 10 MUX_OUT C 9 MUX_OUT D
I2C SDA 2 OVERRIDE# 3 MUX_IN A 4 MUX_IN B 5 MUX_IN C 6 MUX_IN D 7 GND 8
SW00216
DESCRIPTION
The primary function of the 4-bit 2-to-1 I2C multiplexer is to select either a 4-bit input or data from a non-volatile register and drive this value onto the output pins. One additional non-multiplexed register output is also provided. The non-multiplexed output is latched to prevent output value changes during I2C writes to the non-volatile register. A write protect input is provided to enable/disable the ability to write to the non-volatile register. An ``override" input feature forces all outputs to logic 0.
ORDERING INFORMATION
PACKAGES 16-Pin Plastic SO 16-Pin Plastic SSOP 16-Pin Plastic TSSOP TEMPERATURE RANGE 0C to +70C 0C to +70C 0C to +70C OUTSIDE NORTH AMERICA PCA8550D PCA8550DB PCA8550PW NORTH AMERICA PCA8550D PCA8550DB PCA8550PW DH DRAWING NUMBER SOT109-1 SOT338-1 SOT403-1
FUNCTIONAL DESCRIPTION
When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE# signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 1.
The write protect (WP) input is used to control the ability to write the contents of the 5-bit non-volatile register. If the WP signal is logic 0, the I2C bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. The factory default for the contents of the non-volatile register are all logic 0. These stored values can be read or written using the I2C bus (described in the next section). The OVERRIDE#, WP, MUX_IN, and MUX_SELECT signals have internal pullup resistors. See the DC and AC Characteristics for hysteresis and signal spike suppression figures.
1998 Sep 29
2
853-2015 20105
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
PIN DESCRIPTION
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 SYMBOL I2C SCL I2C SDA OVERRIDE# MUX_IN A MUX_IN B MUX_IN C MUX_IN D GND MUX_OUT D MUX_OUT C MUX_OUT B MUX_OUT A MUX_SELECT Selects MUX_IN inputs or register contents for MUX_OUT outputs TTL-level output from non-volatile memory Non-volatile register write-protect Positive voltage rail 2.5V multiplexed out ut 2 5V multi lexed output Common ground voltage rail External in uts to multiplexer inputs multi lexer FUNCTION I2C bus clock Bi-directional I2C bus data Forces all outputs to logic 0
FUNCTION TABLE Table 1. Function table
OVERRIDE # 0 0 MUX_SELECT 0 1 MUX_OUT OUTPUTS All 0's MUX_IN inputs From nonvolatile register MUX_IN inputs NON_MUXED_OUT OUTPUT All 0's Latched
NON_MUXED_OUT1
1
0
From non-volatile register From non-volatile register
1
1
NOTE 1. Latched NON_MIXED_OUT state will be the value present on the NON_MUXED_OUT output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state.
14 15 16 I2C Interface
NON_MUXED_OUT WP VCC
Communicating with this device is initiated by sending a valid address on the I2C bus. The address format (see FIgure 1) is a fixed unique 7-bit value followed by a 1-bit read/write value which determines the direction of the data transfer.
MSB
LSB
1
0
0
1
1
1
0
R/W#
SW00218
Figure 1. I2C Address Byte Following the address and acknowledge bit are 8 data bits which, depending on the read/write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be read from the register if the bit is logic 1. The three high-order bits (see FIgure 2) are logic 0. The next bit is data which is non-multiplexed. The low four bits are the data which will be multiplexed. A write with any of the first three bits non-zero will be aborted. NOTE: 1. To ensure data integrity, the non-volatile register must be internally write protected when VCC to the I2C bus is powered down or VCC to the component is dropped below normal operating levels.
1998 Sep 29
3
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
MSB NONMUXED DATA
LSB
0
0
0
MUX DATA D
MUX DATA C
MUX DATA B
MUX DATA A
SW00219
Figure 2. I2C Data Byte
BLOCK DIAGRAM
10-30k CRESET# MUX_SELECT OVERRIDE#
13
3
5-BIT EEPROM VCC3.3 = 16 GND = 8 100-150k 2 I C iNTERFACE LOGIC SCL I2C CLOCK CHIP SET 2 SDA I2C DATA 10-30k WRITE PROTECT 0 LATCH NMO SELECT
14
NON_MUX_OUT
1
3.3V 4-BIT 2-to-1 MULTIPLEXER
2.5V A20M# MUX_OUT A /FSBM0
12
15
OE#
3.3V
2.5V IGNNE# MUX_OUT B /FSBM1
11 PENTIUM PRO/ PENTIUM II 10 PROCESSORS
4
A20M# MUX_IN A
3.3V
2.5V LINT0/INTR MUX_OUT C /FSBM2
5
IGNNE# MUX_IN B LINT0/INTR MUX_IN C LINT1/NMI MUX_IN D 3.3V
2.5V LINT1/NMI MUX_OUT D /FSBM3
9
6
7
10-30k
1
SW00347
1998 Sep 29
4
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC VI VOUT Tstg PARAMETER DC supply voltage DC input voltage DC output voltage Storage temperature range Note 3 Note 3 CONDITIONS RATING -0.5 to +4.6 -1.5 to VCC +1.5 -0.5 to VCC +0.5 -60 to +150 UNIT V V V C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC SCL, SDA OVERRIDE#, MUX_IN, MUX_SELECT
MUX_OUT, NON_MUXED_OUT
PARAMETER DC supply voltage VIL VIH VOL VIL VIH IOL IOH Input transition rise or fall time Operating temperature
CONDITIONS MIN 3.0 IOL= 3mA -0.5 2.7 -0.5 2.0 MAX 3.6 0.9 4.0 0.4 0.8 4.0 2.0 -2.0 0 0 10 70
UNIT V V
V
mA ns/V C
dt/dv TA
1998 Sep 29
5
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
DC CHARACTERISTICS
LIMITS SYMBOL PARAMETER Temp = 0C to +70C 3.0V < VCC 3.6V MIN VOL IOL (VOL = 0.4V) IOL (VOL = 0.6V) IIL (VIL = 0.4V) IIH (VIH = 2.4V) VHYS1 IIL IIH IIL (VIL = 0.4V) IIH (VIH = 2.4V) VOL (IOL = 100A) VOL (IOL = 2.0mA) VOH (IOH = -100A) VOH (IOH = -1.0mA) VOL (IOL = 100A) VOL (IOL = 2.0mA) VOH (IOH = -100A) VOH (IOH = -2.0mA) Quiescent supply current (VCC = 3.3V) VI = 0V to VCC Quiescent supply current VI = VCC All inputs ESD protection Input diode clamp voltage NOTES: 1. VHYS is the hysteresis of Schmitt-Trigger inputs 2. Human body model 2.0 -1.5 0 -7 -1.5 0.19 -86 -20 -0.72 -0.166 -0.3 -0.3 2.0 1.7 -0.5 -0.5 2.4 2.0 MAX 0.6 3.0 6.0 -32 -12 -267 -100 -2.0 -0.75 0.4 0.7 2.625 2.625 0.4 0.7 3.6 3.6 10 500 10 V mA mA A A V A mA UNIT
SCL, SDA
OVERRIDE#, WP, MUX_SELECT MUX A D
MUX_OUT
V
NON_MUXED_OUT
V
ICC ICC CIN
mA A pF KV V
NON-VOLATILE STORAGE SPECIFICATIONS
Parameter Memory cell data retention Number of memory cell write cycles Specification 10 years min 1,000 cycles min
1998 Sep 29
6
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
AC CHARACTERISTICS
LIMITS SYMBOL TMPD TSOV TOVN TOVM TR TF CL PARAMETER Mux input to output propagation delay MUX_SELECT to output valid OVERRIDE# to NON_MUX output delay OVERRIDE# to mux output delay Output rise time Output fall time Test load capacitance on Muxed/Non-Muxed outputs I2C BUS fSCL TSCH TSCL TDSP TSDS TSDH TICR TICF TBUF TSTS TSTH TSPS CB TW I2C I2C I2C I2C clock frequency I2C I2C clock high time clock low time 10 600 1.3 0 100 0 20 20 1.3 600 600 600 400 TYPICAL = 15 300 300 50 400 KHz ns ns ns ns ns ns ns ns ns ns ns pF ms 1.0 1.0 MIN MAX 20.0 22 15.0 25.0 3.0 3.0 15 UNIT ns ns ns ns ns/V ns/V pF
I2C data spike time I2C data setup time I2C data hold time input rise time (10-400pF bus) input fall time (10-400pF bus)
bus free time between start and stop I2C repeated start condition setup I2C repeated start condition hold I2C stop condition setup I2C bus capacitive load time1
Write cycle
NOTE: 1. WRITE CYCLE time can only be measured indirectly during write cycle. The device will not acknowledge its I2C address.
1998 Sep 29
7
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
1998 Sep 29
8
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
1998 Sep 29
9
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
1998 Sep 29
10
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
NOTES
1998 Sep 29
11
Philips Semiconductors
Product specification
4-bit multiplexed/1-bit latched 5-bit I2C EEPROM
PCA8550
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Date of release: 03-98 Document order number: 9397-750-04606
Philips Semiconductors
1998 Sep 29 12

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